Aldec says it has increased the performance of Riviera 2004.04 over the previous release, yielding as much as a 2x speed-up for mixed VHDL and Verilog designs. This performance increase was achieved by optimising the communication between language compilers and additional optimisation of the VHDL and Verilog compilers individually. Additional performance increases came from the new waveform database structure (.asdb), which has been completely implemented in Riviera 2004.04. It now includes new debugging and graphical interface improvements to provide customers with one of the fastest operating system-independent RTL debugging environments available, according to the company.
Riviera 2004.04 provides improved support for assertion-based verification and includes a new assertion viewer, templates and a language assistant. The graphical assertion viewer helps designers easily identify and utilise the information by showing all assertions in the simulated model. In addition, it provides statistics including the number of assertions that have failed in the current simulation, the number of passed assertions, and the last time a given assertion was violated.
Aldec has also implemented new constructs for Verilog 1364-2001. New Verilog 2001 support includes such constructs as generate-loop, -case, and -conditional statements as well as automatic (re-entrant) tasks/functions. These constructs allow the designer to use a more robust coding style when describing their Verilog design. The IEEE Verilog 1364-2001 standard includes Verilog 1995, 2001 and SystemVerilog, all are supported by Aldec.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]
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